Previously designed methods of interfacing between two subsystems operating at low speeds have been successful in achieving the desired result. In low speed systems, clock skew between subsystems was minimal in that the resultant clock skew was only a portion of the entire clock cycle time. Thus, data was stable long enough to allow a skewed clock to capture the data in a state device and safely meet its setup and hold time requirements.
Interfacing between subsystems becomes more critical as the interfacing subsystems increase their operating speed. One or both of the subsystems may actually be asynchronous, they may both be synchronous on different clocks, simply related or unrelated to each other or they may both be operating under the same clock but there is high clock skew between them. In any of the above situations, the interfacing problem exists.
When data rates are high, there is frequently an interfacing problem because the data from the sending subsystem is not stable long enough to meet the receiving subsystem's state device's setup time requirements. By conventional means, data would be stable for at most one cycle time to the sending subsystem. If the clock skew between two subsystems is greater than this time, it is difficult for the receiver to capture the data.
While the prior art provides adequate means of interfacing between two subsytems, there is a need for advancement. In particular, in a high performance computer system, avoiding this interfacing problem is becoming more difficult as processing speeds are increasing. With increasing speeds of operation, it is imperative to ensure data stability across subsystem boundaries to meet the receiving subsystems data stable time requirements. The prior art does not adequately address these limitations.